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1205 HD66132T (240-channel hi-fas segment driver for dot-matrix graphic lcd display) rev 0.6 march 1996 description the HD66132T is a 240-channel segment driver, which drives a dot matrix liquid crystal graphic system with hi-fas (high-frequency-amp litude selection). the HD66132T operates with low voltages of 5-v lcd drive voltage and 3.3-v logic drive voltage, and therefore, its low current consumption characteristics of liquid crystal cells can be effectively used. the HD66132T, packaged in a fine-pitch slim tape carrier package (slim-tcp), makes it possible to reduce the size of the user area. features hi-fas drive method duty cycle: up to 1/300 lcd drive voltage: 5.5v max 240 lcd drive circuits operating voltage: 3.5 to 5.5v eight data bits shift clock speed ? 25 mhz max/3v ? 40 mhz max/5v display off function slim tcp output lead pitch: 70 to 93 m m user area: 5.5 to 6.66 mm chip enable signal automatic generation standby function
HD66132T 1206 pin arrangement 1 y1 2 y2 239 y239 240 y240 3 y3 4 y4 5 y5 238 y238 237 y237 236 y236 263 262 261 260 259 258 257 256 255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 vml v0l v1l v cc shl eio1 disp d0 d1 d2 d3 d4 d5 d6 d7 cl2 cl1 note: this figure does not specify the tape carrier package dimension. top view m eio2 gnd v1r v0r vmr figure 1 pin arrangement
HD66132T 1207 block diagram lcd drive circuit level shifter latch circuit (2) latch circuit (1) latch circuit (1) shift register y1 to y240 d 0 to d 7 v0l, vml, and v1l cl1 m cl2 shl eio1 eio2 data shifter disp v cc gnd v0r, vmr, and v1r figure 2 block diagram block functions lcd drive circuit the 240-bit lcd drive circuit generates three voltage levels vh, vl, and vm, which drive the lcd panel. one of these three levels is output to the corresponding y pin, depending on the ',63 signal and the combination of the m signal and the data in latch circuit (2). level shifter the level shifter changes logic control signals into lcd drive signals. latch circuit (2) 240-bit latch circuit (2) latches data input from latch circuit (1), and outputs the latched data to the level shifter, both at the falling edge of each clock 1 (cl1) pulse.
HD66132T 1208 latch circuit (1) 240-bit latch circuit (1) latches 8-bit parallel data input via the d0 to d7 pins, and outputs the latched data to latch circuit 2, both at the timing generated by the shift register. shift register the 30-bit shift register generates and outputs data latch signals for latch circuit (1) at the falling edge of each clock 2 (cl2) pulse. data shifter the data shifter shifts the destinations of data output, when necessary.
HD66132T 1209 pin function table 1 pin functions classification symbol pin no. pin name input/ output function power supply v cc gnd 260 244 v cc gnd v cc Cgnd: logic power supply v0l, v0r vml, vmr v1l, v1r 262, 242 263, 241 261, 243 v0l, v0r vml, vmr v1l, v1r input lcd drive level voltage. see figure 3. control signal cl1 247 clock 1 input display data latch signal. the lcd drive signal corresponding to display data is output at the falling edge of this signal. cl2 248 clock 2 input display data latch signal. display data is latched at the falling edge of this signal. m 246 m input changes the lcd drive outputs to ac. d0 to d7 256 to 249 data0 to data7 input when display data is 1 (v cc level), the lcd drive output level is selection level and the liquid crystal display is on, and when 0 (gnd level), they are non-selection level and off, respectively. shl 259 shift left input a control signal to switch the data output destination. see the section of switching data output destination. (,2 258 enable i/o 1 input/ output if shl is v cc level, (,2 inputs the chip enable signal and (,2 outputs the chip enable signal, and if it is gnd level, vice versa enable input: the chip enable input pin of the first HD66132T must be fixed to gnd level, (,2 245 enable i/o 2 input/ output and the rest of chip enable input pins must be connected to the chip enable output pins of he previous HD66132T enable output: the chip enable output pin must be connected to the chip enable input pin of the next HD66132T. ',63 257 disp off input a low ',63 level sets lcd drive outputs y1 to y240 to vm level. lcd drive output y1 to y240 1 to 240 y1 to y240 output either of two levels v0 and v1 is output according to the combination of the m signal and display data when the ',63 pin is set at v cc . see figure 4.
HD66132T 1210 v0 vm v1 figure 3 lcd drive level voltage 1 0 11 00 v0 v1 v1 v0 m d output level figure 4 selection of lcd drive output level
HD66132T 1211 switching data output destination the output destination of data latched by the shl signal is switched (left or right). at this time, input and output of enable signal pins can also be switched. see figure 5. enable input: eio1 enable output: eio2 1st data last data d0 d7 d2 d6 d5 d4 d3 d1 d7 d2 d6 d5 d4 d3 d1 d0 y8 y1 y2 y3 y4 y5 y6 y7 y238 y237 y236 y235 y234 y233 y239 y240 enable input: eio2 enable output: eio1 last data 1st data d7 d0 d5 d1 d2 d3 d4 d6 d0 d5 d1 d2 d3 d4 d6 d7 y8 y1 y2 y3 y4 y5 y6 y7 y238 y237 y236 y235 y234 y233 y239 y240 shl = gnd shl = v cc figure 5 data output destination
HD66132T 1212 operation timing figure 6 shows 8-bit data latch timing when shl = gnd, that is, the (,2 pin is a chip enable input and (,2 pin is a chip enable output. when shl = v cc , the (,2 pin is a chip enable output and (,2 pin is a chip enable input. when a low chip enable signal is input via the (,2 pin, the HD66132T is first released from data standby state, and, at the falling edge of the following cl2 pulse, it is released entirely from standby state and starts latching data. it simultaneously latches eight bits of data at the falling edge of each cl2 pulse. when it has latched 232 bits of data, it sets the (,2 signal low. when it has latched 240 bits of data, it automatically stops and enters standby state, initiating the next HD66132T, as long as its (,2 pin is connected to the (,2 pin of the next HD66132T. the HD66132Ts output one line of data from the y1 to y240 pins at the falling edge of each cl1 pulse. data d1 is output from y1, and d240 from y240 when shl = gnd, and d1 is output from y240, and d240 from y1 when shl = v cc . d240 d233 1 2 30 31 299 300 301 cl2 HD66132T no.1 latches data d 0 d 7 cl1 eio2 (no.1) eio2 (no.2) eio2 (no.3) eio2 (no.10) line 29 d8 d1 d16 d9 28 298 ...... ...... HD66132T no.2 latches data HD66132T no.3 latches data HD66132T no.10 latches data ----- ----- ----- ----- ----- ----- figure 6 data latch timing
HD66132T 1213 application example controller cl1 cl2 m d0 to d7 flm disp power supply circuit v ee v cc gnd vm lcd panel 800 3 600 1/300 duty com1 com2 com3 com599 com600 seg2400 seg2399 seg2398 seg3 seg2 seg1 shl eio1 y1 to y240 HD66132T cl1 cl2 m d0 to d7 disp v cc eio2 gnd (no.10) v1l, v1r vml, vmr v0l, v0r shl eio1 y1 to y240 HD66132T cl1 cl2 m d0 to d7 disp v cc eio2 gnd (no.2) v1l, v1r vml, vmr v0l, v0r shl eio1 y1 to y240 HD66132T cl1 cl2 m d0 to d7 disp v cc eio2 gnd (no.1) v1l, v1r vml, vmr v0l, v0r shl eio1 y1 to y240 HD66132T cl1 cl2 m d0 to d7 disp v cc eio2 gnd (no.20) v1l, v1r vml, vmr v0l, v0r shl eio1 y1 to y240 HD66132T cl1 cl2 m d0 to d7 disp v cc eio2 gnd (no.12) v1l, v1r vml, vmr v0l, v0r shl eio1 y1 to y240 HD66132T cl1 cl2 m d0 to d7 disp v cc eio2 gnd (no.11) v1l, v1r vml, vmr v0l, v0r dio2 x1 to x120 hd66133t vhl,r vll,r vml,r cl m disp v cc shl ch vlcdl, r dio1 dio2 x1 to x120 hd66133t vhl,r vll,r vml,r cl m disp v cc shl ch dio1 v cc v cc gnd gnd veel, r veel, r (no.1) (no.5) v0(seg) vl(com) v1(seg) vh(com) vlcd - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - v cc v cc v cc vlcd1, 2 vlcdl, r notes: 1. to stabilize the power supply, place two 0.1- m f capacitors near each hd66133ts: one between the v cc and gnd pins. and the other between the vlcd and gnd pins. 2. the load must be less than 30 pf between the eio2 and eio1 connections of HD66132Ts. figure 7 application example
HD66132T 1214 absolute maximum ratings *1 item symbol ratings unit note power supply logic circuit v cc C0.3 to +7.0 v 2 and 5 voltage lcd drive circuit vlcd C 0.3 to +7.0 v 2 and 5 input voltage (1) vt1 C0.3 to v cc + 0.3 v 2 and 3 input voltage (2) vt2 C0.3 to v0 + 0.3 v 2 and 4 operating temperature t opr C20 to +75 c storage temperature t stg C40 to +125 c notes: 1. if the lsi is used beyond the above maximum ratings, it may be permanently damaged. it should always be used within its specified operating range for normal operation to prevent malfunction or degraded reliability. 2. the reference point is gnd (0v). 3. applies to logic circuit input pins. 4. applies to the vml, vmr, vil, and vir pins 5. power should be applied to v cc Cgnd first, and then gndCv0, and should be cut off in gndCv0 first, and then gndCv cc .
HD66132T 1215 electrical characteristics dc characteristics 1 (v cc = 2.7 to 4.5v, v0Cgnd = 3.5 to 5.5v, and ta = C20 to +75 c, unless otherwise stated) item symbol applicable pin min. typ. max. unit conditions note input high level voltage vih cl1, cl2, shl, m, (,2 , (,2 , ',63 , 0.7 v cc v cc v input low level voltage vil and d0 to d7 0 0.3 v cc v output high level voltage voh (,2 and (,2 v cc C 0.4 v i oh = C0.4 ma output low level voltage vol (,2 and (,2 0.4 v i ol = 0.4 ma viCyj on resistance r on y1 to y240, v0l, and v0r 0.5 1.0 k w i on = 150 m a1 y1 to y240, vml, and vmr 1.0 2.0 k w y1 to y240, v1l, and v1r 0.5 1.0 k w input leakage current (1) i il1 cl1, cl2, shl, m, (,2 , (,2 , ',63 , and d0 to d7 C5 5 m a vin = v cc Cgnd input leakage current (2) i il2 vml, vmr, v1l, and v1r C100 25 m a vin = v0Cgnd current consumption (1) i cc v cc tbd ma v cc = 3.0 v f cl2 = 25 mhz 2 current consumption (2) i v0 v0l and v0r tbd ma f cl1 = 100 khz f m = 75 hz current consumption (3) i st v cc tbd ma 2 and 3
HD66132T 1216 dc characteristics 2 (v cc = 2.7 to 4.5v, v0Cgnd = 3.5 to 5.5v, and ta = C20 to +75 c, unless otherwise stated) item symbol applicable pin min. typ. max. unit conditions note input high level voltage vih cl1, cl2, shl, m, (,2 , (,2 , ',63 , 0.7 v cc v cc v input low level voltage vil and d0 to d7 0 0.3 v cc v output high level voltage voh (,2 and (,2 v cc C 0.4 v i oh = C0.4 ma output low level voltage vol (,2 and (,2 0.4 v i ol = 0.4 ma viCyj on resistance r on y1 to y240, v0l, and v0r 0.5 1.0 k w i on = 150 m a1 y1 to y240, vml, and vmr 1.0 . k w y1 to y240, v1l, and v1r 0.5 1.0 k w input leakage current (1) i il1 cl1, cl2, shl, m, (,2 , (,2 , ',63 , and d0 to d7 C5 5 m a vin = v cc Cgnd input leakage current (2) i il2 vml, vmr, v0l, and v0r C100 100 m a vin = v0Cgnd current consumption (1) i cc v cc tbd ma v cc = 5.0v f cl2 = 40 mhz 2 current consumption (2) i v0 v0l and v0r tbd ma f cl1 = 160 khz f m = 75 hz current consumption (3) i st v cc tbd ma 2 and 3 notes: 1 indicates the resistance between one of the pins y1Cy240 and one of the voltage supply pins, when load current is applied to the y pin; defined under the following conditions: v0Cgnd = 6v vm = (vlcdCgnd)/2 v1 = gnd + 1 v1 should be near the gnd level, and the vm should be near the middle voltage between v1 and v0. 1 should be within the range of d v = 3 v0, which is the range within which ron, the lcd drive circuits output impedance, is stable. see figure 8. 2. input and output currents are excluded. when a cmos input is left floating, excess current flows from the power supply through the input circuit. to avoid this, vih and vil must be held at v cc and gnd, respectively. 3. standby current.
HD66132T 1217 v0 gnd vm v1 d v = 0.3 v0 figure 8 relationship between driver output waveforms and each level voltage
HD66132T 1218 ac characteristics 1 (v cc = 2.7 to 4.5v, v0Cgnd = 3.5 to 5.5v, and ta = C20 to +75 c, unless otherwise stated) *1 item symbol applicable pins min. max. unit note clock cycle time t cyc cl2 40 ns clock high level width (1) t cwh2 cl2 15 ns clock low level width (1) t cwl2 cl2 15 ns clock high level width (2) t cwh1 cl1 25 ns clock setup time t scl cl1 and cl2 100 ns clock hold time t hcl cl1 and cl2 100 ns clock rise time t r cl1 and cl2 30 ns 2 clock fall time t f cl1 and cl2 30 ns 2 data setup time t ds d0 to d7, and cl2 10 ns data hold time t dh d0 to d7, and cl2 10 ns m phase difference t cm m 300 ns output delay time (1) t pd1 cl1, and y1 to y240 500 ns output delay time (2) t pd2 m, and y1 to y240 500 ns notes: 1. the load must be less than 30 pf between (,2 and (,2 connections of HD66132Ts. 2. clock rise time (t r ) and clock fall time (t f ) must satisfy the following condition: t r and t f < (t cyc C t cwh2 C t cwl2 )/2 (1) t r and t f 30 ns
HD66132T 1219 ac characteristics 2 (v cc = 4.5 to 5.5v, v0Cgnd = 4.5 to 5.5v, and ta = C20 to +75 c, unless otherwise stated) *1 item symbol applicable pins min. max. unit note clock cycle time t cyc cl2 25 ns clock high level width (1) t cwh2 cl2 10 ns clock low level width (1) t cwl2 cl2 10 ns clock high level width (2) t cwh1 cl1 25 ns clock setup time t scl cl1 and cl2 100 ns clock hold time t hcl cl1 and cl2 100 ns clock rise time t r cl1 and cl2 20 ns 2 clock fall time t f cl1 and cl2 20 ns 2 data setup time t ds d0 to d7, and cl2 6 ns data hold time t dh d0 to d7, and cl2 6 ns m phase difference t cm m 300 ns output delay time (1) t pd1 cl1, and y1 to y240 500 ns output delay time (2) t pd2 m, and y1 to y240 500 ns notes: 1. the load must be less than 30 pf between (,2 and (,2 connections of HD66132Ts. 2. clock rise time (t r ) and clock fall time (t f ) must satisfy the following condition: t r and t f < (t cyc C t cwh2 C t cwl2 )/2 t r and t f 20 ns
HD66132T 1220 cl2 d0 to d7 t r t cwh2 t f t cwl2 t cyc t ds t dh 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc y (n) t pd1 t pd2 cl1 m 0.7 v cc 0.3 v cc 0.3 v cc 0.8 v0 0.2 v1 0.8 v0 0.2 v1 m cl1 cl2 t cwh1 t cm 0.7 v cc 0.3 v cc t scl t hcl 0.7 v cc 0.3 v cc 0.3 v cc figure 9 ac characteristics

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